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EMIF08-VID01C2
8 line low capacitance EMI filter and ESD protection
Main product characteristics
Where EMI filtering in ESD sensitive equipment is required:

LCD and camera for mobile phones Computers and printers Communication systems MCU Boards
Description
The EMIF08-VID01C2 is an 8 line highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The Flip-Chip packaging means the package size is equal to the die size. This filter includes ESD protection circuitry, which prevents damage to the application when it is subjected to ESD surges up to 15 kV.
12 11 10 987 I6
GND
Coated Flip-Chip package
Pin configuration (Bump side)
654 I4
GND
321 I2
GND
Benefits

I8
GND
I7
I5
I3
I1
A B C
High efficiency EMI filter (-33 dB @ 900 MHz) Low line capacitance suitable for high speed data bus Low serial resistance for camera impedance adaptation Optimized PCB space consuming: 1.29 mm x 3.92 mm Very thin package: 0.695 mm Coating resin on back side and lead free package High efficiency in ESD suppression on inputs pins (IEC 61000-4-2 level 4). High reliability offered by monolithic integration High reducing of parasitic elements through integration & wafer level packaging.
O8
O7
O6
O5
O4
O3
O2
O1
Complies with following standards:
IEC 61000-4-2
level 4 input pins 15 kV 8 kV level 1 output pins 2 kV 2 kV (air discharge) (contact discharge (air discharge) (contact discharge
MIL STD 883E - Method 3015-6 Class 3
October 2006
Rev 4
www.st.com
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Characteristics
EMIF08-VID01C2
1
Characteristics
Figure 1. Basic cell configuration
Input R Output
R = 100 Cline = 16 pF typ. @ 3 V
Table 1.
Symbol Vpp Tj Top Tstg
Absolute ratings (limiting values)
Parameter ESD discharge IEC 61000-4-2 air discharge ESD discharge IEC 61000-4-2 contact discharge Maximum junction temperature Operating temperature range Storage temperature range Value 15 8 125 -40 to +85 -55 to +150 Unit kV kV C C C
Table 2.
Symbol VBR IRM VRM R Cline
Electrical characteristics (Tamb = 25 C)
Parameters
I
Breakdown voltage Leakage current @ VRM
IRM V VRM VBR
Stand-off voltage Series resistance between input and output Input capacitance per line
Symbol VBR IRM RI/O Cline IR = 1 mA
Test conditions
Min 6
Typ 8
Max 10 500
Unit V nA pF
VRM = 3 V per line I = 10 mA VR = 3 V DC, 1 MHz 80 100 16
120 19
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EMIF08-VID01C2
Characteristics
Figure 2.
dB
0 -5 -10 -15
S21 (dB) attenuation measurement Figure 3.
dB
0 -10 -20 -30 -40
Analog crosstalk measurement
-20
-50
-25
-60
-30 -35 -40
-70 -80 -90
F (Hz)
-45 100k 1M 10M 100M 1G
F (Hz)
100k 1M 10M 100M 1G
-100
Figure 4.
ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input Vin and one output Vout
Figure 5.
ESD response to IEC 61000-4-2 (- 15 kV air discharge) on one input Vin and one output Vout
Input
Input 10V/d
10V/d
Output 10V/d
Output 10V/d 200ns/d
200ns/d
Figure 6.
Line capacitance versus applied voltage
CLINE (pF)
28 26 24 22 20 18 16 14 12 10 0 1 2
VLINE (V)
3 4 5
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Ordering information scheme
EMIF08-VID01C2
2
Ordering information scheme
EMIF
EMI Filter Number of lines X: resistance (Ohms) Z: capacitance value / 10 pF or Application (3 letters) and Version (2 digits) C: Coated flip chip
vv
-
xxx zz
C
y
1: Pitch = 500 m, Bump = 315 m 2: Lead free Pitch = 500 m, Bump = 315 m
3
Package information
Figure 7. Flip-Chip Dimensions
315 m +/- 50
500m +/-50 250m +/-50 -
435 m +/-50
695m +/- 70 -
50 1 m
3.92 mm +/-50m -
Figure 8.
Marking
Figure 9.
Footprint recommendation
Dot, ST logo xx = marking z = manufacturing location yww = date code (y = year ww = week)
Copper pad Diameter: 250m recommended, 300m max
(R)
E
Solder stencil opening: 330m
xxz xxz yww yww
Solder mask opening recommendation: 340m min for 300m copper pad diameter
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1.29 mm +/-50m .29
+/ 50
EMIF08-VID01C2 Figure 10. Flip-Chip tape and reel specification
Dot identifying Pin A1 location 4 +/- 0.1
Ordering information
O 1.5 +/- 0.1
1.75 +/- 0.1 3.5 +/- 0.1
0.78 max
All dimensions in mm
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
8 +/- 0.3
ST E
ST E
ST E
xxx yww
User direction of unreeling
xxx yww
xxx yww
4 +/- 0.1
4
Ordering information
Ordering code EMIF08-VID01C2 Marking GS Package Flip-Chip Weight 7.4mg Base qty 4000 Delivery mode 7" Tape and reel
5
Revision history
Date 13-Jul-2005 11-Aug-2005 31-May-2006 26-Oct-2006 Revision 1 2 3 4 Initial release. Fonts changed in Figures 7, 8, and 9. Reformatted to current standards. Depth dimension changed in Figure 10. Base quantity changed to 4000 in Ordering information Changes
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EMIF08-VID01C2
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